MC74HC175A |
RFQ for MC74HC175A Required Field |
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| Technical/Catalog Information | MC74HC175ADG |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC |
| Function | Reset |
| Number of Bits per Element | 4 |
| Number of Elements | 1 - Single |
| Current - Output High, Low | 5.2mA, 5.2mA |
| Output Type | Differential |
| Trigger Type | Positive Edge |
| Type | D-Type Bus |
| Packaging | Tube |
| Operating Temperature | -55°C ~ 125°C |
| Delay Time - Propagation | 28ns |
| Frequency - Clock | 35MHz |
| Voltage - Supply | 2 V ~ 6 V |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | MC74HC175ADG MC74HC175ADG |
| Product | Manufacturers | Pack | D/C |
| MC74HC175A | - | 99/P2 | SOP |
The MC74HC175A is identical in pinout to the LS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of four D flipflops with common Reset and Clock inputs, and separate D inputs. Reset (activelow) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive going edge of the Clock input.
Features |
| • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 mA• High Noise Immunity Characteristic of CMOS Devices• In Compliance with the Requirements Defined by JEDEC Standard No. 7A• Chip Complexity 166 FETs or 41.5 Equivalent Gates |
| Symbol | Parameter | Value | Unit |
| vcc | DC Supply Voltage (Referenced to GND) | 0.5 to +7.0 | V |
| VIN | DC Input Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| VOUT | DC Output Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| LIN | DC Input Current, per Pin | ±20 | mA |
| IOUT | DC Onput Current, per Pin | ±25 | mA |
| ICC | DC Supply Current Per Supply Pin | ±50 | mA |
| PD | Power dissipation in still air piastic DIP SOIC package |
750 500 450 |
mW |
| TSTG | Storage Temperature | 65 to +150 | °C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 | °C |
